80286 microprocessor architecture:
The 80286 microprocessor was developed for multi-user systems with multitasking applications, including communications and real-time process control.8086 microprocessor had 134,000 transistors and consisted of four independent units: address unit, bus unit, instruction unit and an execution unit.
Things to be noted:
- CPU speed: (6-25) MHZ
- RAM: 16 MB
- Advance version of 8086
- Total functional units present: 4
1) Address unit
2) Bus unit
3) Instruction unit
4) Execution unit
- It has a 16-bit data bus
- It has 24-bit address bus
- It contains total 68 pins in a chip
- It contains 16-bit registers
- It can access virtual memory up to 1 GB
- It has two addressing modes:
1) Real addressing mode
2) The protected virtual addressing mode
- The 80286 microprocessor was developed for multi-user systems with multitasking applications, including communications and real-time process control.
- It had 134,000 transistors and consisted of four independent units: address unit, bus unit, instruction unit and an execution unit.
- 80286 microprocessor was produced in a 68-pin package including PLCC (Plastic Leaded Chip Carrier), LCC (Leadless chip carrier) and PGA (Pin Grid Array) packages.
- The Intel 80286 microprocessor had a 24-bit address bus and it is able to address up to 16 MB of RAM, compared to 1 MB for its predecessor. However, the cost and initial rarity of software using the memory above 1 MB meant that 80286 computers were rarely shipped with more than one megabyte of RAM.
80286 Architecture contains 4 separate processing units.
1. Bus Unit (BU)
2. Instruction Unit (IU)
3. Address Unit (AU)
4. Execution Unit (EU)
Fig: a block diagram of 80286 microprocessor
Bus Unit (BU):
It has address latches, data transceivers, bus interface and circuitry, instruction pre-fetcher, processor extension interface and 6-byte instruction queue.
- To perform all memory and input/output read and write functions.
- To pre-fetch the instruction bytes.
- For the purpose of control and transfer of data to and from processor extension devices such as 80287 math co-processor.
- Whenever BU is not using the buses for the operation, it pre-fetches the instruction bytes and put them is a 6-byte pre-fetch queue.
Instruction Unit (IU):
It has 3 decoded instruction queue and an instruction decoder.
- It fully decodes up to three pre-fetched instructions and holds them in a queue. So that EU can access them.
- It also supports the processor to speed up, as pipelining of instruction is done.
Execution Unit (EU):
It includes ALU, registers and the Control unit. General purpose, index, pointer, flag register and 16 –bit Machine Status Word (MSW) are the registers present in EU.
- In order to sequentially execute the instructions received from the instruction unit.
- ALU result is either stored in register bank or sent over the data bus.
Address Unit (AU):
Address unit consists of segment registers, offset address and a physical address adder.
- To compute the physical address which will be sent out to the memory or I/O by BU.
- 80286 operate in two different modes
1. Real address mode
2. Protected virtual address mode.
- When used in Real address mode, address unit computes the address with segment base and offset like 8086. Segment register is CS, DS, ES and SS hold a base address. IP, BP, SI, DI, SP hold offset.
- Maximum physical space allowed in real mode is 1MB.
- When 80286 operate in protected mode, the address unit acts as a memory management unit(MMU).
- All 24 address lines used and can access up to 16MB of physical memory.
- If the descriptor table scheme is used it can address up to 1GB of virtual memory
Register organization of 80286:
The registers of 80286 CPU are as same as in 8086, namely
1. 16-bit of general purpose registers which are (AX, BX, CX, DX)
2. Four 16-bit segment registers which are(CS, SS, DS, ES)
3. Status and control registers which are (SP, BP, SI, DI)
4. Instruction Pointer (IP)
5. Two 16-bit register – FLAGS, MSW
6. Two 16-bit register – LDTR and TR
7. Two 48-bit register – GDTR and IDTR
Figure: 80286 Register Set
The flag register reflects the results of logical and arithmetic instruction
Fig: 80286 flag register
- Flag register is of 32 – bit. other bits are undefined/reserved.
- System flags: reflect the current status of the machine.
i. IOPL – I/O Privilege Level flag: 2 –bits are used in protected mode. It holds the privilege level from 0 to 3. ‘0’ refers to the highest privilege whereas ‘3’ refers to a lower privilege level.
ii. NT: Nested Task flag: NT flag is used in protected mode. The bit is set when one task invokes another task.
Salient features of 80286 microprocessor:
- The 80286 microprocessor is the first member of the family of advanced microprocessors which has memory management and protection abilities.
- The CPU, of 80286 with its 24-bit address bus contains 16 Mb of physical memory. Various versions of 80286 are available that run on 12.5 MHz, 10 MHz and 8 MHz clock frequencies.
- 80286 is upwardly compatible with 8086 in terms of the instruction set.
- 80286 have two operating modes which are real address mode and virtual address mode.
- In real address mode, the 80286 can address up to 1Mb of physical memory address like 8086.
- In virtual address mode, 80286 can address up to 16 Mb of physical memory address space and 1 GB of virtual memory address space.
- The instruction set of 80286 includes the instructions of 8086 and 80186.
- 80286 has some extra instructions to support the operating system and memory management.
- In protected virtual address mode, it is source code compatible with 8086.
- The 80286 performs five times faster than the standard 8086.